DS680 Datasheet, PDF (8/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
PowerPC Processor Switching Characteristics
Consult UG018, PowerPC 405 Processor Block Reference Guide for further information.
Table 14: PowerPC 405 Processor Clocks Absolute AC Characteristics
Description
Characteristics when APU Not Used
CPMC405CLOCK frequency^(1,4)
CPMDCRCLK⁽³⁾
CPMFCMCLK⁽³⁾
JTAGC405TCK frequency⁽²⁾
PLBCLK⁽³⁾
BRAMDSOCMCLK⁽³⁾
BRAMISOCMCLK⁽³⁾
Characteristics when APU Used
CPMC405CLOCK frequency^(1,4)
CPMDCRCLK⁽³⁾
CPMFCMCLK⁽³⁾
JTAGC405TCK frequency⁽²⁾
PLBCLK⁽³⁾
BRAMDSOCMCLK⁽³⁾
BRAMISOCMCLK⁽³⁾
Speed Grade
-10
Min
Max
Units
0
350
MHz
0
350
MHz
–
–
MHz
0
175
MHz
0
350
MHz
0
350
MHz
0
350
MHz
0
233
MHz
0
233
MHz
0
233
MHz
0
116.5
MHz
0
233
MHz
0
233
MHz
0
233
MHz
Notes:
1. Worst-case DCM output clock jitter is included in these specifications.
2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent,
and will be much less.
3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the
CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK,
CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However,
the achievable maximum is system dependent.
4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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