DS680 Datasheet, PDF (18/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

R
Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Table 27: OLOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ODCK / T_OCKD
T_OOCECK / T_OCKOCE
T_OSRCK / T_OCKSR
T_OTCK / T_OCKT
T_OTCECK / T_OCKTCE
Combinatorial
T_ODQ
T_OTQ
Sequential Delays
T_IOSRON
T_OCKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
D1/D2 pins setup/hold with respect to CLK
OCE pin setup/hold with respect to CLK
SR/REV pin setup/hold with respect to CLK
T1/T2 pins setup/hold with respect to CLK
TCE pin setup/hold with respect to CLK
D1 to OQ out
T1 to TQ out
REV pin to TQ out
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Speed Grade
-10
Units
0.75/–0.22
ns
0.77/–0.33
ns
1.42/–0.55
ns
0.75/–0.22
ns
0.77/–0.33
ns
0.76
ns
0.76
ns
1.64
ns
0.59
ns
1.64
ns
2.03
ns
0.70
ns Min
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
18