DS680 Datasheet, PDF (7/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Switching Characteristics
Switching characteristics are specified on a per-speed- grade
basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Table 13 correlates the current status of each Virtex-4QV
device with a corresponding speed specification version
1.67 designation.
Table 13: Virtex-4QV Device Speed Grade
Designations
Device
Speed Grade Designations
Advance Preliminary Production
XQR4VSX55
-10
XQ4RVFX60
-10
XQR4VFX140
-10
XQR4VLX200
-10
Because individual family members are produced at
different times, the migration from one category to another
depends completely on the status of the fabrication process
for each device.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotate to the
simulation net list. Unless otherwise noted, values apply to
all Virtex-4QV FPGAs.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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