DS680 Datasheet, PDF (35/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Production Stepping
The Virtex-4 FPGA stepping identification system denotes
the capability improvement of production released devices.
By definition, devices from one stepping are functional
supersets of previous devices. Bitstreams compiled for a
device with an earlier stepping are guaranteed to operate
correctly in subsequent device steppings.
New device steppings can be shipped in place of earlier device
steppings. Existing production designs are guaranteed on new
device steppings. To take advantage of the capabilities of a
newer device stepping, customers are able to order a new
stepping version and compile a new bitstream.
Production devices are marked with a stepping version, with
the exception of some step 1 devices. Designs should be
compiled with a CONFIG STEPPING parameter set to a
specific stepping version.
This parameter is set in the UCF file:
CONFIG STEPPING = “#”;
Where
# = the stepping version
Table 56 shows the JTAG ID code by step.
Table 56: JTAG ID Code by Step
Device
ID Code
XQR4VSX55
4
XQ4RVFX60
8
XQR4VFX140
4
XQR4VLX200
2 or 5
Stepping
2
1
1
0 or 3
Current Production Virtex-4 FPGA Devices
Table 57 summarizes the current production device stepping.
Table 57: Current Production Devices
Device Stepping
Example Ordering Code
Device steppings shipped when ordered per
Example Ordering Code
Capability Improvements
CONFIG STEPPING parameter
(must be set in UCF file)
Minimum Software Required
Minimum Speed Specification Required
XQR4VFX60-CF1144V
Step 2
Step 1 or 2 only (see Table 56)
• T_CONFIG requirement is removed
• DCM_RESET requirement is removed
• DCM_INPUT_CLOCK_STOP requirement is removed by a
macro (automatically inserted by ISE software)
“1”
ISE 7.1i SP4
1.58
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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