DS680 Datasheet, PDF (17/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 26: ILOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ICE1CK / T_ICKCE1
T_ICECK / T_ICKCE
T_IRSTCK / T_ICKRST
T_IINCCK / T_ICKINC
T_ISRCK / T_ICKSR
T_IDOCK / T_IOCKD
T_IDOCKD / T_IOCKDD
Combinatorial
T_IDI
T_IDID
Sequential Delays
T_IDLO
T_IDLOD
T_ICKQ
T_ICE1Q
T_RQ
T_GSRQ
Set/Reset
T_RPW
CE1 pin setup/hold with respect to CLK
DLYCE pin setup/hold with respect to CLKDIV
DLYRST pin setup/hold with respect to CLKDIV
DLYINC pin setup/hold with respect to CLKDIV
SR/REV pin setup/hold with respect to CLK
D pin setup/hold with respect to CLK without Delay
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to O pin propagation delay, no Delay
D pin to O pin propagation delay
(IOBDELAY_TYPE = DEFAULT)
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to Q1 pin using flip-flop as a latch without Delay
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
Global set/reset to Q outputs
Minimum pulse width, SR/REV inputs
Speed Grade
Units
-10
0.79/–0.23
ns
0.23/0.16
ns
–0.02/0.54
ns
0.01/0.51
ns
1.59/–0.56
ns
0.34/–0.10
ns
8.84/–5.99
ns
1.09/–0.63
ns
0.24
ns
7.96
ns
0.99
ns
0.71
ns
9.21
ns
1.45
ns
0.72
ns
1.27
ns
2.44
ns
2.03
ns
0.70
ns, Min
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
17