DS680 Datasheet, PDF (32/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

R
Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
System-Synchronous Switching Characteristics
Virtex-4QV FPGA Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 48. Values are expressed in nanoseconds unless otherwise noted.
Table 48: Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM
Symbol
Description
Device
Speed Grade
-10
LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.⁽³⁾
XQR4VSX55
4.14
T_ICKOFDCM
Global Clock and OFF with DCM
XQR4VFX60
3.96
XQR4VFX140
4.59
XQR4VLX200
4.46
Units
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
3. Clock to out has +320 ps offset for operation above 100° C.
Table 49: Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM
Symbol
Description
Device
Speed Grade
-10
LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM.⁽²⁾
XQR4VSX55
9.54
T_ICKOF
Global Clock and OFF without DCM
XQR4VFX60
XQR4VFX140
9.11
10.02
XQR4VLX200
10.14
Units
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Clock to out has +250 ps offset for operation above 100° C
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
32