DS680 Datasheet, PDF (28/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Table 39: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Cont’d)
Symbol
Description
Input Clocks (High Frequency Mode)
CLKIN_FREQ_DLL_HF_MS_MIN
CLKIN_FREQ_DLL_HF_MS_MAX
CLKIN_FREQ_FX_HF_MS_MIN
CLKIN_FREQ_FX_HF_MS_MAX
PSCLK_FREQ_HF_MS_MIN
PSCLK_FREQ_HF_MS_MAX
CLKIN (using DLL outputs)^(1,3,4)
CLKIN (using DFS outputs only)^(2,3,4)
PSCLK
Speed Grade
-10
150
400
50
300
1
400
Units
MHz
MHz
MHz
MHz
KHz
MHz
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
5. The DCM must be reset if the clock input clock stops for more than 100 ms.
Table 40: Input Clock Duty Cycle Input Tolerance
Symbol
Description
CLKIN_PSCLK_PULSE_RANGE_1
PSCLK only
CLKIN_PSCLK_PULSE_RANGE_1_50
CLKIN_PSCLK_PULSE_RANGE_50_100
CLKIN_PSCLK_PULSE_RANGE_100_200
PSCLK and CLKIN
CLKIN_PSCLK_PULSE_RANGE_200_400
Frequency Range
< 1 MHz
1 – 50 MHz
50 – 100 MHz
100 – 200 MHz
200 – 400 MHz
Value
25 – 75
25 – 75
30 – 70
40 – 60
45 – 55
Units
%
%
%
%
%
Table 41: Input Clock Tolerances
Symbol
Description
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN_CYC_JITT_DLL_LF
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_CYC_JITT_FX_LF
CLKIN (using DFS outputs)⁽²⁾
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_FX_HF
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Input Clock Period Jitter (Low Frequency Mode)
CLKIN_PER_JITT_DLL_LF
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_PER_JITT_FX_LF
CLKIN (using DFS outputs)⁽²⁾
Input Clock Period Jitter (High Frequency Mode)
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Feedback Clock Path Delay Variation
CLKFB_DELAY_VAR_EXT
CLKFB off-chip feedback
Speed Grade
-10
Units
±300
ps
±300
ps
±150
ps
±150
ps
±1.0
ns
±1.0
ns
±1.0
ns
±1.0
ns
±1.0
ns
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. If both DLL and DFS outputs are used, follow the more restrictive specifications.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
28