DS680 Datasheet, PDF (33/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Virtex-4QV FPGA Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 50. Values are expressed in nanoseconds unless otherwise noted.
Table 50: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM
Symbol
Description
Device
Input Setup-and-Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.^(1,4)
XQR4VSX55
T_PSDCM / T_PHDCM
No Delay Global Clock and IFF
with DCM⁽²⁾
XQR4VFX60
XQR4VFX140
XQR4VLX200
Speed Grade
-10
Units
1.73/–0.13
ns
1.53/0.12
ns
1.52/0.82
ns
1.76/0.41
ns
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative
to the Global Clock input signal with the slowest route and heaviest load.
2. These measurements include:
CLK0 DCM jitter
IFF = input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
4. Hold time has +200 ps offset for operation above 100° C.
Table 51: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-10
Units
Example Data Input Setup-and-hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock Buffer.^(1,3,4)
XQR4VSX55
–0.09/1.52
ns
T_{PSDCM_0} /T_{PHDCM_0}
No Delay Global Clock and IFF with
DCM in Source-Synchronous Mode⁽²⁾
XQR4VFX60
XQR4VFX140
–0.25/1.77
ns
–0.32/2.56
ns
XQR4VLX200
0.00/2.06
ns
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter.
Package skew is not included in these measurements.
2. IFF = input flip-flop
3. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the
values shown in "IOB Switching Characteristics(1,2)," page 11.
4. Setup time has +100 ps offset for operation above 100° C.
Table 52: Global Clock Setup and Hold for LVCMOS25 Standard, Without DCM
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
XQR4VSX55
T_PSFD / T_PHFD
Full Delay Global Clock and IFF
without DCM⁽²⁾
XQR4VFX60
XQR4VFX140
XQR4VLX200
Speed Grade
-10
Units
3.02/0.98
ns
3.58/0.62
ns
3.51/1.71
ns
4.32/0.82
ns
Notes:
1. Setup time is measured relative to the global clock input signal with the fastest route and the lightest load. Hold time is measured relative to
the global clock input signal with the slowest route and heaviest load.
2. IFF = input flip-flop or latch
3. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed best-case, but if a “0” is
listed, there is no positive hold time.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
33