DS680 Datasheet, PDF (25/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Configuration Switching Characteristics
Table 37: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
T_PL
Program latency
T_POR
Power-on-reset
T_ICCK
CCLK (output) delay
T_PROGRAM
Program pulse width
Master/Slave Serial Mode Programming Switching
T_DCC / T_CCD
T_DSCK / T_SCKD
T_CCO
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
T_CCH
T_CCL
High time
Low time
F_{CC_SERIAL}
Maximum frequency, master mode with respect to nominal CCLK.
F_MCCTOL
Frequency tolerance, master mode with respect to nominal CCLK.
F_{MAX_SLAVE}
Slave mode external CCLK
SelectMAP Mode Programming Switching
T_SMDCC / T_SMCCD
T_SMCSCC / T_SMCCCS
T_SMCCW / T_SMWCC
T_SMCKBY
SelectMAP setup/hold
CS_B setup/hold
RDWR_B setup/hold
BUSY propagation delay
F_{CC_SELECTMAP}
Maximum frequency, master mode with respect to nominal CCLK.
F_MCCTOL
Frequency tolerance, master mode with respect to nominal CCLK.
Boundary-Scan Port Timing Specifications
T_TAPTCK
T_TCKTAP
T_TCKTDO
TMS and TDI setup time before TCK
TMS and TDI hold time after TCK
TCK falling edge to TDO output valid
F_TCK
Maximum configuration TCK clock frequency
F_TCKB
Maximum Boundary-Scan TCK clock frequency
Speed Grade
Units
-10
0.5
T_PL + 10
500
400
µs/fram
e, max
ms,
max
ns, min
ns, min
1.0/1.0
1.0/1.0
8.0
2.0
2.0
80
±50
80
ns, min
ns, min
ns, max
ns, min
ns, min
MHz,
max
%
MHz
3.0/0.0
2.0/0.5
8.0/1.0
8.0
80
±50
ns, min
ns, min
ns, min
ns, max
MHz,
max
%
1.5
ns, min
2.0
ns, min
8.0
ns, max
66
MHz,
max
50
MHz,
max
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
25