DS680 Datasheet, PDF (19/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 28: ISERDES Switching Characteristics
Symbol
Description
Setup/Hold for Control Lines
T_{ISCCK_BITSLIP} / T_{ISCKC_BITSLIP}
T_{ISCCK_CE} / T_{ISCKC_CE(2)}
T_{ISCCK_CE2} / T_{ISCKC_CE2(2)}
T_{ISCCK_DLYCE} / T_{ISCKC_DLYCE}
T_{ISCCK_DLYINC} / T_{ISCKC_DLYINC}
T_{ISCCK_DLYRST} / T_{ISCKC_DLYRST}
T_{ISCCK_REV}
T_{ISCCK_SR}
Setup/Hold for Data Lines
T_{ISDCK_D} / T_{ISCKD_D}
T_{ISDCK_DDR} / T_{ISCKD_DDR}
Sequential Delays
T_{ISCKO_Q}
Propagation Delays
T_{ISDO_DO_IOBDELAY_IFD}
T_{ISDO_DO_IOBDELAY_NONE}
T_{ISDO_DO_IOBDELAY_BOTH}
T_{ISDO_DO_IOBDELAY_IBUF}
BITSLIP pin setup/hold with respect to CLKDIV
CE pin setup/hold with respect to CLK (for CE1)
CE pin setup/hold with respect to CLKDIV (for CE2)
DLYCE pin setup/hold with respect to CLKDIV
DLYINC pin setup/hold with respect to CLKDIV
DLYRST pin setup/hold with respect to CLKDIV
REV pin setup with respect to CLK
SR pin setup with respect to CLKDIV
D pin setup/hold with respect to CLK
(IOBDELAY = IBUF or NONE)
D pin setup/hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK⁽¹⁾
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK at DDR mode⁽¹⁾
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLKDIV to out at Q pin
D input to DO output pin (IOBDELAY = IFD)
D input to DO output pin (IOBDELAY = NONE)
D input to DO output pin (IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin⁽¹⁾ (IOBDELAY = BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D input to DO output pin (IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin⁽¹⁾ (IOBDELAY = IBUF,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
Notes:
1. Recorded at 0 tap value.
2. T_{ISCCK_CE2} and T_{ISCKC_CE2} are reported as T_{ISCCK_CE} / T_{ISCKC_CE} in TRCE report.
Speed Grade
-10
Units
0.40/–0.13
ns
0.69/–0.25
ns
0.16/–0.02
ns
0.23/0.16
ns
0.01/0.51
ns
–0.02/0.54
ns
1.23
ns
0.92
ns
0.34/–0.11
ns
8.84/–6.51
ns
1.08/–0.68
ns
0.34/–0.11
ns
8.84/–6.51
ns
1.08/–0.68
ns
0.85
ns
0.24
ns
0.24
ns
7.96
ns
0.99
ns
7.96
ns
0.99
ns
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
19