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DS680 Datasheet, PDF (4/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs
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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
SelectIO DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Unless otherwise noted, values for IOL and IOH are guaranteed over
the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are
chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the
respective VOL and VOH voltage levels shown. Other standards are sample tested.
Table 7: Select I/O DC Input and Output Levels
IOSTANDARD
Attribute V, Min
VIL
V, Max
VIH
V, Min
V, Max
VOL
V, Max
VOH
V, Min
IOL
IOH
mA
mA
LVTTL
–0.2
0.8
2.0
3.45
0.4
2.4
Note(3) Note(3)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3(5)
PCI66_3(5)
PCI-X(5)
GTLP
GTL
HSTL I(2)
HSTL II(2)
HSTL III(2)
HSTL IV(2)
DIFF HSTL II(2)
SSTL2 I
SSTL2 II
DIFF SSTL2 II
SSTL18 I
SSTL18 II
DIFF SSTL18 II
–0.2
–0.3
–0.3
–0.3
–0.2
–0.2
–0.2
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
2.0
0.7
1.7
35% VCCO
35% VCCO
30% VCCO
30% VCCO
35% VCCO
VREF – 0.1
VREF – 0.05
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.1
50% VCCO – 0.1
VREF – 0.15
VREF – 0.15
50% VCCO – 0.15
VREF – 0.125
VREF – 0.125
50% VCCO – 0.125
65% VCCO
65% VCCO
50% VCCO
50% VCCO
50% VCCO
VREF + 0.1
VREF + 0.05
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
50% VCCO + 0.1
VREF + 0.15
VREF + 0.15
50% VCCO + 0.15
VREF + 0.125
VREF + 0.125
50% VCCO + 0.125
3.45
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO
VCCO
VCCO
–
–
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
0.4
0.4
0.4
0.4
10% VCCO
10% VCCO
10% VCCO
0.6
0.4
0.4
0.4
0.4
0.4
0.4
VTT – 0.61
VTT – 0.81
0.5
VTT – 0.47
VTT – 0.60
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.45
VCCO – 0.45
90% VCCO
90% VCCO
90% VCCO
–
–
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VTT + 0.61
VTT + 0.81
VCCO – 0.5
VTT + 0.47
VTT + 0.60
VCCO – 0.4
Note(3) Note(6)
Note(3) Note(3)
Note(4) Note(4)
Note(4) Note(6)
1.5
–0.5
1.5
–0.5
1.5
–0.5
36
–
32
–
8
–8
16
–16
24
–8
48
–8
–
–
8.1
–8.1
16.2 –16.2
–
–
6.7
–6.7
13.4 –13.4
–
–
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCIX, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
6. LVCMOS15 4 mA, LVCMOS33 6 mA, LVCMOS33 8 mA have reduced drive strength (IOH) by 20%.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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