DS680 Datasheet, PDF (27/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Clock Buffers and Networks
Table 38: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
T_{BCCCK_CE} / T_{BCCKC_CE(1)}
T_{BCCCK_S} / T_{BCCKC_S(1)}
T_{BCCKO_O}
Maximum Frequency
Description
CE pins setup/hold
S pins setup/hold
BUFGCTRL delay
Speed Grade
-10
0.35/0.00
0.35/0.00
0.90
Units
ns
ns
ns
F_MAX
Global clock tree
400
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
DCM and PMCD Switching Characteristics
DCM in Maximum Range (MR) Mode is not supported for operation beyond industrial temperature range.
Table 39: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Description
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MS_MIN
CLKOUT_FREQ_1X_LF_MS_MAX
CLKOUT_FREQ_2X_LF_MS_MIN
CLKOUT_FREQ_2X_LF_MS_MAX
CLKOUT_FREQ_DV_LF_MS_MIN
CLKOUT_FREQ_DV_LF_MS_MAX
CLKOUT_FREQ_FX_LF_MS_MIN
CLKOUT_FREQ_FX_LF_MS_MAX
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MS_MIN
CLKIN_FREQ_DLL_LF_MS_MAX
CLKIN_FREQ_FX_LF_MS_MIN
CLKIN_FREQ_FX_LF_MS_MAX
PSCLK_FREQ_LF_MS_MIN
PSCLK_FREQ_LF_MS_MAX
Outputs Clocks (High Frequency Mode)
CLKOUT_FREQ_1X_HF_MS_MIN
CLKOUT_FREQ_1X_HF_MS_MAX
CLKOUT_FREQ_2X_HF_MS_MIN
CLKOUT_FREQ_2X_HF_MS_MAX
CLKOUT_FREQ_DV_HF_MS_MIN
CLKOUT_FREQ_DV_HF_MS_MAX
CLKOUT_FREQ_FX_HF_MS_MIN
CLKOUT_FREQ_FX_HF_MS_MAX
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)^(1,3,4,5)
CLKIN (using DFS outputs only)^(2,3,4)
PSCLK
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
Speed Grade
-10
Units
32
MHz
150
MHz
64
MHz
300
MHz
2
MHz
100
MHz
32
MHz
210
MHz
32
MHz
150
MHz
1
MHz
210
MHz
1
KHz
400
MHz
150
MHz
400
MHz
300
MHz
400
MHz
9.4
MHz
267
MHz
210
MHz
300
MHz
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
27