DS680 Datasheet, PDF (34/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
ChipSync Source-Synchronous Technology Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4QV FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 53: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
-10
Units
T_{DCD_CLK}
Global Clock Tree Duty Cycle
Distortion⁽¹⁾
All
150
ps
XQR4VSX55
190
ps
T_CKSKEW
Global Clock Tree Skew⁽²⁾
XQR4VFX60
XQR4VFX140
190
ps
350
ps
XQR4VLX200
350
ps
T_{DCD_BUFIO}
I/O clock tree duty cycle distortion
All
I/O clock tree skew across one clock
All
region
100
ps
50
ps
T_BUFIOSKEW
I/O clock tree skew across multiple clock
All
regions
50
ps
T_{DCD_BUFR}
T_{BUFIO_MAX_FREQ}
T_{BUFR_MAX_FREQ}
Regional clock tree duty cycle distortion
All
I/O clock tree MAX frequency
All
Regional clock tree MAX frequency
All
250
ps
500
MHz
250
MHz
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T_CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
Table 54: Sample Window
Symbol
T_SAMP
T_{SAMP_BUFIO}
Description
Sampling Error at Receiver Pins⁽¹⁾
Sampling Error at Receiver Pins using BUFIO⁽²⁾
Device
All
All
Speed Grade
-10
550
450
Units
ps
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 55: ChipSync™ Technology Pin-to-Pin Setup/Hold and Clock to Out
Symbol
Description
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T_PSCS / T_PHCS
Setup/hold of I/O clock across multiple clock regions
Pin-to-Pin Clock to Out Using BUFIO
T_ICKOFCS
Clock-to-Out of I/O clock across multiple clock regions
Speed Grade
Units
-10
–0.44/1.17
ns
5.02
ns
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
34