DS680 Datasheet, PDF (31/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Table 44: Miscellaneous Timing Parameters (Cont’d)
Symbol
Description
Input Signal Requirements
DCM_RESET⁽³⁾
DCM_INPUT_CLOCK_STOP
Minimum duration that RST must be held asserted
Maximum duration that RST can be held asserted⁽⁴⁾
Maximum duration that CLKIN and CLKFB can be
stopped^(5,6)
Speed Grade
-10
Units
200
ms
10
sec
100
ms
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. CLKIN must be present and stable during the DCM_RESET.
4. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in answer record 21127 for
support of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
5. For production step 1 LX and SX devices, use the design solutions described in answer record 21127 for support of longer durations of
stopped clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small
macro to support longer durations of stopped clocks.
6. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
Table 45: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
2
32
CLKFX_DIVIDE
1
32
Table 46: DCM Switching Characteristics
Symbol
Description
T_{DMCCK_PSEN} / T_{DMCKC_PSEN}
T_{DMCCK_PSINCDEC} / T_{DMCKC_PSINCDEC}
T_{DMCKO_PSDONE}
PSEN setup/hold
PSINCDEC setup/hold
Clock to out of PSDONE
Table 47: PMCD Switching Characteristic
Symbol
Description
T_{PMCCCK_REL} / T_{PMCCKC_REL}
T_{PMCCO_CLK{A1,B,C,D}}
T_{PMCCKO_CLK{A1,B,C,D}}
PMCD_CLK_SKEW
CLKIN_FREQ_PMCD_CLKA_MAX
CLKIN_PSCLK_PULSE_RANGE
PMCD_REL_HIGH_PULSE_MIN
PMCD_RST_HIGH_PULSE_MIN
REL setup/hold for all outputs
RST assertion to clock output deassertion
Max clock propagation delay of PMCD for all outputs
Max phase between all outputs assuming all inputs
Max input/output frequency
Max duty-cycle input tolerance (same as DCM)
Min pulse width for REL
Min pulse width for RST
Notes:
1. Refer to Table 40, page 28 parameter: CLKIN_PSCLK_PULSE_RANGE.
Speed Grade
-10
1.07/0.00
1.07/0.00
0.69
Units
ns
ns
ns
Speed Grade
-10
0.60/0.00
4.50
5.20
±150
400
Note⁽¹⁾
1.25
1.25
Units
ns
ns
ns
ps
MHz
ns
ns
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
31