DS680 Datasheet, PDF (22/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
Table 32: CLB Distributed RAM Switching Characteristics
Symbol
Description
Sequential Delays
T_SHCKO
Clock CLK to X outputs (WE active)
T_SHCKOF5
Clock CLK to F5 output (WE active)
Setup and Hold Times Before/After Clock CLK
T_DS / T_DH
T_AS / T_AH
T_WS / T_WH
Clock CLK
BX/BY data inputs (DI)
F/G address inputs
WE input (SR)
T_WPH
T_WPL
T_WC
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Speed Grade
-10
Units
2.08
ns, max
1.98
ns, max
1.80/–0.88
1.13/–0.29
1.42/–0.47
ns, min
ns, min
ns, min
0.69
ns, min
0.70
ns, min
0.98
ns, min
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. T_SHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Table 33: CLB Shift Register Switching Characteristics
Symbol
Description
Sequential Delays
T_REG
Clock CLK to X/Y outputs
T_REGXB
Clock CLK to XB output via MC15 LUT output
T_REGYB
Clock CLK to YB output via MC15 LUT output
T_CKSH
Clock CLK to Shiftout
T_REGF5
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
T_WS / T_WH
T_DS / T_DH
Clock CLK
WE input (SR)
BX/BY data inputs (DI)
T_WPH
T_WPL
Minimum pulse width, High
Minimum pulse width, Low
Speed Grade
-10
Units
2.57
ns, max
2.04
ns, max
2.17
ns, max
1.99
ns, max
2.47
ns, max
1.12/–0.62
1.75/–1.11
ns, min
ns, min
0.69
ns, min
0.70
ns, min
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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