DS680 Datasheet, PDF (6/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, for example, a 100Ω resistor between the two receiver pins.
The V_OH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the
Virtex-4 FPGA User Guide: Chapter 6, SelectIO Resources.
Table 11: LVPECL DC Specifications
Symbol
DC Parameter
Min
V_OH
V_OL
V_ICM
V_IDIFF
Output High Voltage
Output Low Voltage
Input Common-Mode Voltage
Differential Input Voltage^(1,2)
V_CC – 1.025
V_CC – 1.81
0.6
0.100
Notes:
1. Recommended input maximum voltage not to exceed V_CC0 + 0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Typ
1.545
0.795
Max
V_CC – 0.88
V_CC – 1.62
2.2
1.5
Units
V
V
V
V
Interface Performance Characteristics
Table 12: Interface Performances
Networking Applications
SFI-4.1 (SDR LVDS Interface)⁽⁵⁾
SPI-4.2 (DDR LVDS Interface)
Memory Interfaces
DDR⁽¹⁾
DDR2⁽²⁾
QDR II SRAM⁽³⁾
RLDRAM II⁽⁴⁾
Description
Speed Grade
-10
500 MHz
800 Mb/s
426 Mb/s
510 Mb/s
514 Mb/s
524 Mb/s
Notes:
1. Performance defined using design implementation described in application note XAPP709: DDR SDRAM Controller Using Virtex-4 FPGA
Devices.
2. Performance defined using design implementation described in application note XAPP702: DDR2 Controller Using Virtex-4 Devices.
3. Performance defined using design implementation described in application note XAPP703: QDR II SRAM Interface for Virtex-4 Devices.
4. Performance defined using design implementation described in application note XAPP710: Synthesizable CIO DDR RLDRAM II Controller
for Virtex-4 FPGAs.
5. 644 MHz not supported for operating temperatures above 100°C.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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