DS680 Datasheet, PDF (23/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 34: Block RAM Switching Characteristics
Symbol
Description
Speed Grade
-10
Units
Sequential Delays
T_{RCKO_DORA}
T_{RCKO_DOA}
Setup and Hold Times Before Clock CLK
T_{RCCK_ADDR} / T_{RCKC_ADDR}
T_{RDCK_DI} / T_{RCKD_DI}
T_{RCCK_EN} / T_{RCKC_EN}
T_{RCCK_REGCE} / T_{RCKC_REGCE}
T_{RCCK_SSR} / T_{RCKC_SSR}
T_{RCCK_WE} / T_{RCKC_WE}
Maximum Frequency
Clock CLK to DOUT output (without output register)⁽²⁾
Clock CLK to DOUT output (with output register)⁽³⁾
ADDR inputs
DIN inputs⁽⁴⁾
EN input⁽⁵⁾
CE input of output register
RST input
WEN input
2.10
ns, max
0.92
ns, min
0.43/0.33
0.23/0.33
0.52/0.33
0.32/0.33
0.32/0.33
0.75/0.33
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
F_MAX
F_MAX
Write first and no change mode
Read first mode
400.00
400.00
MHz
MHz
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. T_{RCKO_DORA} includes T_{RCKO_DOWA}, T_{RCKO_DOPAR}, and T_{RCKO_DOPAW} as well as the B port equivalent timing parameters.
3. T_{RCKO_DOA} includes T_{RCKO_DOPA} as well as the B port equivalent timing parameters.
4. T_{RCKO_DI} includes both A and B inputs as well as the parity inputs of A and B.
5. Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must
be stable during the specified set-up time. Do not create an asynchronous input on an enabled port address.
Table 35: FIFO Switching Characteristics
Symbol
Description
Speed Grade
-10
Units
Sequential Delays
T_{FCKO_DO}
T_{FCKO_FLAGS}
T_{FCKO_POINTERS}
Setup and Hold Times Before Clock CLK
T_{FDCK_DI} / T_{FCKD_DI}
T_{FCCK_EN} / T_{FCKC_EN}
Reset Delays
T_{FCO_FLAGS}
Maximum Frequency
Clock CLK to DO output⁽²⁾
Clock CLK to FIFO flags outputs⁽³⁾
Clock CLK to FIFO pointer outputs⁽⁴⁾
DI input⁽⁵⁾
Enable inputs⁽⁶⁾
Reset RST to FLAGS⁽⁷⁾
0.92
ns, max
1.19
ns, max
1.48
ns, max
0.23/0.33
0.84/0.33
ns, min
ns, min
1.68
ns, max
F_MAX
FIFO in all modes
400.00
MHz
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. T_{FCKO_DO} includes parity output (T_{FCKO_DOP}).
3. T_{FCKO_FLAGS} includes these parameters: T_{FCKO_AEMPTY}, T_{FCKO_AFULL}, T_{FCKO_EMPTY}, T_{FCKO_FULL}, T_{FCKO_RDERR}, T_{FCKO_WRERR.}
4. T_{FCKO_POINTERS} includes both T_{FCKO_RDCOUNT} and T_{FCKO_WRCOUNT.}
5. T_{FDCK_DI} includes parity inputs (T_{FDCK_DIP}).
6. T_{FCCK_EN} includes both WRITE and READ enable.
7. T_{FCO_FLAGS} includes these flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
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