DS680 Datasheet, PDF (24/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
XtremeDSP Switching Characteristics
Table 36: XtremeDSP™ Switching Characteristics
Symbol
Description
Setup and Hold of CE Pins
T_{DSPCCK_CE} / T_{DSPCKC_CE}
T_{DSPCCK_RST} / T_{DSPCKC_RST}
Setup and Hold Times of Data
T_{DSPDCK_{AA, BB, CC}} /
T_{DSPCKD_{AA, BB, CC}}
T_{DSPDCK_{AM, BM}} /
T_{DSPCKD_{AM, BM}}
Sequential Delays
T_{DSPCKO_PP}
T_{DSPCKO_PM}
Combinatorial
T_{DSPDO_{AP, BP}L}
Maximum Frequency
F_MAX
Setup/hold of all CE inputs of the DSP48 slice
Setup/hold of all RST inputs of the DSP48 slice
Setup/hold of {A, B, C} input to {A, B, C} register
Setup/hold of {A, B} input to M register
Clock to out from P register to P output
Clock to out from M register to P output
From {A, B} input to P output
(LEGACY_MODE = MULT18X18)
From {A, B} register to P register
(LEGACY_MODE = MULT18X18)
Fully Pipelined
Speed Grade
-10
Units
0.49/0.12
ns
0.40/0.12
ns
0.32/0.29
ns
2.28/0.00
ns
0.79
ns
2.98
ns
4.41
ns
253.94
400.00
MHz
MHz
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
24