DS680 Datasheet, PDF (20/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Input Delay Switching Characteristics
Table 29: Input Delay Switching Characteristics
Symbol
Description
T_{IDELAYRESOLUTION}
T_{IDELAYTOTAL_ERR}
IDELAY Chain Delay Resolution
Cumulative delay at a given tap⁽³⁾
T_{IDELAYCTRLCO_RDY}
F_{IDELAYCTRL_REF}
IDELAYCTRL_REF_PRECISION ⁽²⁾
T_{IDELAYCTRL_RPW}
T_{IDELAYPAT_JIT}
Reset to Ready for IDELAYCTRL (Maximum)
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
Pattern dependent period jitter in delay chain for clock
pattern
Pattern dependent period jitter in delay chain for random
data pattern (PRBS 23)
Speed Grade
-10
75
[(tap −1) x 75 +34]
±0.07[(tap −1) x
75 +34]
3.00
200
±10
50.0
Units
ps
ps
µs
MHz
MHz
ns
0
Note (1)
10 ± 2
Note (1)
Notes:
1. Units in ps peak-to-peak per tap.
2. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, “SelectIO Logic
Resources.”
3. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
Output Serializer/Deserializer Switching Characteristics
Table 30: OSERDES Switching Characteristics
Symbol
Description
Setup/Hold
T_{OSDCK_D} / T_{OSCKD_D}
T_{OSDCK_T} / T_{OSCKD_T(1)}
T_{OSDCK_T2} / T_{OSCKD_T2(1)}
T_{OSCCK_OCE} / T_{OSCKC_OCE}
T_{OSCCK_S}
T_{OSCCK_TCE} / T_{OSCKC_TCE}
Sequential Delays
D input setup/hold with respect to CLKDIV
T input setup/hold with respect to CLK
T input setup/hold with respect to CLKDIV
OCE input setup/hold with respect to CLK
SR (Reset) input setup with respect to CLKDIV
TCE input setup/hold with respect to CLK
T_{OSCKO_OQ}
T_{OSCKO_TQ}
Combinatorial
Clock to out from CLK to OQ
Clock to out from CLK to TQ
T_{OSDO_TTQ}
T_{OSCO_OQ}
T_{OSCO_TQ}
T input to TQ out
Asynchronous reset to OQ
Asynchronous reset to TQ
Notes:
1. T_{OSDCK_T2} and T_{OSCKD_T2} are reported as T_{OSDCK_T} / T_{OSCKD_T} in TRCE report.
Speed Grade
-10
Units
0.50/–0.03
ns
0.62/–0.16
ns
0.50/–0.03
ns
0.64/0.03
ns
0.96
ns
0.64/0.03
ns
0.59
ns
0.59
ns
0.76
ns
1.64
ns
1.64
ns
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
20