DS893 Datasheet, PDF (76/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Date
10/12/2015
07/27/2015
05/29/2015
07/10/2014
Version
1.3
1.2
1.1
1.0
Description of Revisions
Updated description of I_CCADC in Table 3.
Updated the description in Power-On/Off Power Supply Sequencing.
Updated Table 20, Table 21, Table 22, Table 27, and Table 28 with speed specifications for
Vivado Design Suite 2015.3 v1.18. Production release (Table 22) of the XCVU095 and
XCVU080 devices in the -3 (1.0V), -2 (0.95V), and -1 (0.95V) speed/temperature grades.
Added protocols to Table 57. Updated V_CMOUTDC in Table 64. Added data to Table 72 and
Table 73.
In Table 86, revised values for F_SCCK, F_EMCCK, F_RBCCK, and F_TCK and added the Startup
Timing section.
In Table 18 and Table 19 updated Note 2, Note 3, and Note 4.
Updated Table 20 and Table 38 through Table 43 with speed specifications for Vivado
Design Suite 2015.2 v1.16.
Updated the STARTUPE3 Ports descriptions in Table 86. Updated Note 1 in Table 87.
Entire data sheet is updated. Some of the highlights are noted in this revision history
although it is not comprehensive.
Updated Note 2 and Note 3 in Table 1 and Note 3, Note 4, and Note 6 in Table 2. Added
data and Note 2 to Table 3. Updated Note 3 in Table 6. Revised the Power-On/Off Power
Supply Sequencing section. Updated the descriptions in Table 8. Revised the V_OCM
maximum for MINI_LVDS_25 and RSDS_25 in Table 12. Revised the V_ICM specifications
in Table 14. Removed rows from Table 16 and Table 17. Removed V_OH and V_OL rows,
revised the V_OCM maximum, and revised V_ICM in Table 18. Removed V_OH and V_OL rows
and revised V_ICM in Table 19. Updated Table 20, Table 27, and Table 28 with speed
specifications for Vivado Design Suite 2015.1 v1.15. Added Note 1 to Table 29.
Added the section: I/O Standard Adjustment Measurement Methodology. Updated
F_REFCLK in Table 33. Revised MMCM_F_INMAX and MMCM_T_LOCKMAX in Table 36. Updated the
descriptions and PLL_F_INMAX in Table 37. Added a discussion on the data in the device
pin-to-pin parameter tables on page 39 and page 41. Updated Table 44. Updated the
package information in Table 45. Updated V_CMOUTDC and added Note 2 in Table 46. Added
Table 48 and Table 52. Updated both Table 55 and Table 56. Updated and combined the
protocol characteristic sections into the GTH Transceiver Electrical Compliance section.
Updated some of the maximum values for F_GTYMAX, F_GTYQRANGE1, and F_GTYQRANGE2 in
Table 66. Updated F_RXIN2 (data width conditions for internal logic) in Table 71. Updated
and combined the protocol characteristic sections into the GTY Transceiver Electrical
Compliance section. Revised the values for F_{LBUS_CLK} in Table 80. Revised F_CORECLK and
Note 1 in Table 82. Updated the On-Chip Sensor Accuracy, On-chip reference, and Note 5
in Table 83. In Table 86, added more speed specifications, updated T_POR, T_PL, F_MCCKTOL,
and F_RBCCK, added the STARTUPE3 Ports section, and added Note 1.
Initial Xilinx release.
DS893 (v1.7.1) April 4, 2016
Product Specification
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