DS893 Datasheet, PDF (42/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 43: Global Clock Input Setup and Hold With PLL
Symbol
Description
Device
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
Units
-3
-1H
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^(1)(2)(3)
T_{PSPLLCC_VU065}
T_{PHPLLCC_VU065}
Global clock input and input
flip-flop (or latch) with PLL.
Setup
XCVU065
Hold
–0.70
2.03
–0.70
2.27
–0.70
2.27
–0.70
2.63
ns
ns
T_{PSPLLCC_VU080}
T_{PHPLLCC_VU080}
Setup
–0.94 –0.94 –0.94 –0.94 ns
XCVU080
Hold
2.14
2.36
2.36
2.71
ns
T_{PSPLLCC_VU095}
T_{PHPLLCC_VU095}
Setup
–0.94 –0.94 –0.94 –0.94 ns
XCVU095
Hold
2.14
2.36
2.36
2.71
ns
T_{PSPLLCC_VU125}
T_{PHPLLCC_VU125}
Setup
–0.67 –0.67 –0.67 –0.67 ns
XCVU125
Hold
2.03
2.27
2.27
2.64
ns
T_{PSPLLCC_VU160}
T_{PHPLLCC_VU160}
Setup
–0.67 –0.67 –0.67 –0.67 ns
XCVU160
Hold
2.03
2.27
2.27
2.64
ns
T_{PSPLLCC_VU190}
T_{PHPLLCC_VU190}
Setup
–0.67 –0.67 –0.67 –0.67 ns
XCVU190
Hold
2.03
2.27
2.27
2.64
ns
T_{PSPLLCC_VU440}
T_{PHPLLCC_VU440}
Setup
–1.16
N/A
–1.16 –1.16 ns
XCVU440
Hold
3.03
N/A
3.44
3.99
ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 44: Sampling Window
Description
Speed Grades and V_CCINT Operating Voltages
1.0V
0.95V
Units
T_{SAMP_BUFG(1)}
T_{SAMP_NATIVE_DPA}
T_{SAMP_NATIVE_BISC}
-3
-1H
-2
-1
510
610
610
610
ps
100
100
100
125
ps
60
60
60
85
ps
Notes:
1. This parameter indicates the total sampling error of the Virtex UltraScale FPGAs DDR input registers, measured across
voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’
edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase
shift resolution. These measurements do not include package or clock tree skew.
DS893 (v1.7.1) April 4, 2016
Product Specification
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