DS893 Datasheet, PDF (38/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
PLL Switching Characteristics
Table 37: PLL Specification⁽¹⁾
Symbol
Description
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
Units
-3 -1H -2
-1
PLL_F_INMAX
PLL_F_INMIN
PLL_F_INJITTER
Maximum input clock frequency
Minimum input clock frequency
Maximum input clock period jitter
Input duty cycle range: 70–399 MHz
1066 933 933 800 MHz
70
70
70
70 MHz
< 20% of clock input period or 1 ns Max
35–65
%
PLL_F_INDUTY
Input duty cycle range: 400–499 MHz
Input duty cycle range: >500 MHz
40–60
%
45–55
%
PLL_F_VCOMIN
Minimum PLL VCO frequency
PLL_F_VCOMAX
Maximum PLL VCO frequency
PLL_T_{STATPHAOFFSET} Static phase offset of the PLL outputs⁽²⁾
PLL_T_OUTJITTER
PLL output jitter
PLL_T_OUTDUTY
PLL CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B
duty-cycle precision⁽⁴⁾
600
1335
0.12
600
1335
0.12
600
1335
0.12
Note 3
600
1200
0.12
0.165 0.20 0.20 0.20
MHz
MHz
ns
ns
PLL_T_LOCKMAX
PLL_F_OUTMAX
PLL maximum lock time
PLL maximum output frequency at
CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B
PLL maximum output frequency at CLKOUTPHY
850
2670
100
725 725
2670 2670
630
2400
µs
MHz
MHz
PLL_F_OUTMIN
PLL minimum output frequency at
CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B⁽⁵⁾
PLL minimum output frequency at CLKOUTPHY
4.69 4.69 4.69 4.69
2 x VCO mode: 1200
1 x VCO mode: 600
0.5 x VCO mode: 300
MHz
MHz
PLL_RST_MINPULSE
PLL_F_PFDMAX
PLL_F_PFDMIN
PLL_F_BANDWIDTH
Minimum reset pulse width
Maximum frequency at the phase frequency detector
Minimum frequency at the phase frequency detector
PLL bandwidth at typical
5.00
667.5
70
15
5.00
667.5
70
15
5.00
667.5
70
15
5.00
600
70
15
ns
MHz
MHz
MHz
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS893 (v1.7.1) April 4, 2016
Product Specification
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