DS893 Datasheet, PDF (6/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)
Symbol
Description
Min
Typ⁽¹⁾
Max Units
Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_40.
–50%
40
50%
Ω
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_48.
–50%
48
50%
Ω
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_60.
–50%
60
50%
Ω
Programmable input termination to V_CCO where
R⁽⁷⁾
ODT = RTT_40.
Programmable input termination to V_CCO where
ODT = RTT_48.
–50%
40
50%
Ω
–50%
48
50%
Ω
Programmable input termination to V_CCO where
ODT = RTT_60.
–50%
60
50%
Ω
Programmable input termination to V_CCO where
ODT = RTT_120.
–50%
120
50%
Ω
Programmable input termination to V_CCO where
ODT = RTT_240.
–50%
240
50%
Ω
Uncalibrated programmable on-die termination in HR I/O banks (measured per JEDEC specification).
R⁽⁷⁾
Internal V_REF
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_40.
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_48.
Thevenin equivalent resistance of programmable input
termination to V_CCO/2 where ODT = RTT_60.
50% V_CCO
70% V_CCO
–50%
40
50%
Ω
–50%
48
50%
Ω
–50%
60
50%
Ω
V_CCO x
0.49
V_CCO x
0.50
V_CCO x
0.51
V
V_CCO x
0.69
V_CCO x
0.70
V_CCO x
0.71
V
Differential
termination
n
r
Programmable differential termination (TERM_100).
Temperature diode ideality factor.
Temperature diode series resistance.
–
100
–
Ω
–
1.002
–
–
–
2
–
Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. For HP I/O banks with a V_CCO of 1.8V and separated V_CCO and V_{CCAUX_IO} power supplies, the I_L maximum current is 70 µA.
3. This measurement represents the die capacitance at the pad, not including the package.
4. Maximum value specified for worst case process at 25°C.
5. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
6. VRP resistor tolerance is (240Ω ±1%).
7. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
DS893 (v1.7.1) April 4, 2016
Product Specification
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