DS893 Datasheet, PDF (64/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 73: GTY Transceiver Receiver Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
J_{T_SJ25.78}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ16.375}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ15}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ14.1}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ13.1}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ12.5_QPLL} Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ12.5_CPLL} Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ11.3_QPLL} Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ10.32_QPLL} Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ10.32_CPLL} Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ9.8}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ8.0_QPLL}
Sinusoidal jitter (QPLL)⁽³⁾
J_{T_SJ8.0_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ6.6_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ5.0}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ4.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ4.00L}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.75}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.20}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ2.5}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ1.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ500}
Sinusoidal jitter (CPLL)⁽³⁾
SJ Jitter Tolerance with Stressed Eye⁽²⁾
25.78 Gb/s
16.375 Gb/s
15.0 Gb/s
14.1 Gb/s
13.1 Gb/s
12.5 Gb/s
12.5 Gb/s
11.3 Gb/s
10.32 Gb/s
10.32 Gb/s
9.8 Gb/s
8.0 Gb/s
8.0 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
4.0 Gb/s
3.75 Gb/s
3.2 Gb/s⁽⁴⁾
2.5 Gb/s⁽⁵⁾
1.25 Gb/s⁽⁶⁾
500 Mb/s
0.25
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.44
0.42
0.44
0.44
0.44
0.45
0.45
0.45
0.50
0.50
0.50
J_{T_TJSE3.2}
Total jitter with stressed eye⁽⁷⁾
3.2 Gb/s
0.7
J_{T_TJSE6.6}
6.6 Gb/s
0.7
J_{T_SJSE3.2}
Sinusoidal jitter with stressed eye^{(7) 3.2 Gb/s}
0.7
J_{T_SJSE6.6}
6.6 Gb/s
0.7
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10^–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
–
UI
–
UI
–
UI
–
UI
DS893 (v1.7.1) April 4, 2016
Product Specification
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