DS893 Datasheet, PDF (40/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 40: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
Units
-3
-1H
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
T_ICKOFMMCMCC Global clock input and output flip-flop with XCVU065 1.36
1.61
1.61
1.93
ns
MMCM.
XCVU080 1.36
1.59
1.59
1.85
ns
XCVU095 1.36
1.59
1.59
1.85
ns
XCVU125 1.36
1.61
1.61
1.94
ns
XCVU160 1.36
1.61
1.61
1.94
ns
XCVU190 1.36
1.61
1.61
1.94
ns
XCVU440 1.37
N/A
1.62
1.88
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. MMCM output jitter is already included in the timing calculation.
Table 41: Global Clock Input to Output Delay With PLL
Symbol
Description
Device
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
T_{ICKOF_PLL_CC} Global clock input and output flip-flop with
PLL.
XCVU065
XCVU080
4.70
4.99
5.38
5.70
5.38
5.70
6.23
6.49
XCVU095 4.99
5.70
5.70
6.49
XCVU125 4.70
5.38
5.38
6.31
XCVU160 4.70
5.38
5.38
6.31
XCVU190 4.70
5.38
5.38
6.31
XCVU440 5.70
N/A
6.53
7.65
Units
ns
ns
ns
ns
ns
ns
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. PLL output jitter is already included in the timing calculation.
DS893 (v1.7.1) April 4, 2016
Product Specification
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