DS893 Datasheet, PDF (22/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
IOB Pad Input, Output, and 3-State
Table 27 (high-range IOB (HR)) and Table 28 (high-performance IOB (HP)) summarizes the values of
standard-specific data input delay adjustments, output delays terminating at pads (based on standard)
and 3-state delays.
• T_{INBUF_DELAY_PAD_I} is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The
delay varies depending on the capability of the SelectIO input buffer.
• T_{OUTBUF_DELAY_O_PAD} is the delay from the O pin to the IOB pad through the output buffer of an IOB
pad. The delay varies depending on the capability of the SelectIO output buffer.
• T_{OUTBUF_DELAY_TD_PAD} is the delay from the T pin to the IOB pad through the output buffer of an IOB
pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output
buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than
T_{OUTBUF_DELAY_TD_PAD} when the DCITERMDISABLE pin is used. In HR I/O banks, the on-die termination
turn-on time is always faster than T_{OUTBUF_DELAY_TD_PAD} when the INTERMDISABLE pin is used.
Table 27: IOB High Range (HR) Switching Characteristics
I/O Standards
BLVDS_25
DIFF_HSTL_I_18_F
DIFF_HSTL_I_18_S
DIFF_HSTL_I_F
DIFF_HSTL_I_S
DIFF_HSTL_II_18_F
DIFF_HSTL_II_18_S
DIFF_HSTL_II_F
DIFF_HSTL_II_S
DIFF_HSUL_12_F
DIFF_HSUL_12_S
DIFF_SSTL12_F
DIFF_SSTL12_S
DIFF_SSTL135_F
DIFF_SSTL135_S
DIFF_SSTL135_R_F
DIFF_SSTL135_R_S
DIFF_SSTL15_F
DIFF_SSTL15_S
DIFF_SSTL15_R_F
DIFF_SSTL15_R_S
DIFF_SSTL18_I_F
DIFF_SSTL18_I_S
DIFF_SSTL18_II_F
DIFF_SSTL18_II_S
T_{INBUF_DELAY_PAD_I}
1.0V
0.95V
-3 -1H -2
-1
0.46 0.58 0.58 0.64
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
0.42 0.53 0.53 0.57
T_{OUTBUF_DELAY_O_PAD}
1.0V
0.95V
-3 -1H -2
-1
1.37 1.37 1.37 1.62
0.71 0.71 0.71 0.90
0.83 0.83 0.83 1.02
0.73 0.73 0.73 0.92
0.77 0.77 0.77 0.96
0.80 0.80 0.80 0.99
0.83 0.83 0.83 1.03
0.71 0.71 0.71 0.91
0.80 0.80 0.80 0.99
0.73 0.73 0.73 0.92
0.82 0.82 0.82 1.01
0.70 0.70 0.70 0.89
1.04 1.04 1.04 1.26
0.70 0.70 0.70 0.88
0.77 0.77 0.77 0.96
0.72 0.72 0.72 0.91
0.80 0.80 0.80 1.00
0.66 0.66 0.66 0.85
0.78 0.78 0.78 0.98
0.73 0.73 0.73 0.92
0.81 0.81 0.81 1.01
0.74 0.74 0.74 0.94
0.86 0.86 0.86 1.05
0.71 0.71 0.71 0.90
0.83 0.83 0.83 1.03
T_{OUTBUF_DELAY_TD_PAD}
1.0V
0.95V
Units
-3 -1H -2
-1
1.39 1.40 1.40 1.66 ns
0.82 0.82 0.82 1.06 ns
0.93 0.94 0.94 1.16 ns
0.90 0.90 0.90 1.14 ns
0.95 0.98 0.98 1.23 ns
0.95 0.98 0.98 1.23 ns
1.01 1.03 1.03 1.28 ns
0.87 0.87 0.87 1.11 ns
0.95 0.96 0.96 1.20 ns
0.73 0.73 0.73 0.92 ns
0.82 0.82 0.82 1.01 ns
0.81 0.81 0.81 1.02 ns
1.04 1.04 1.04 1.26 ns
0.86 0.87 0.87 1.09 ns
0.93 0.94 0.94 1.18 ns
0.83 0.84 0.84 1.06 ns
0.93 0.93 0.93 1.17 ns
0.81 0.82 0.82 1.05 ns
0.96 0.96 0.96 1.20 ns
0.86 0.86 0.86 1.09 ns
0.93 0.94 0.94 1.18 ns
0.92 0.93 0.93 1.18 ns
0.86 0.86 0.86 1.05 ns
0.87 0.88 0.88 1.11 ns
0.99 1.04 1.04 1.29 ns
DS893 (v1.7.1) April 4, 2016
Product Specification
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