DS893 Datasheet, PDF (31/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 30: Input Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
V_L(1)(2)
V_H(1)(2)
(1^V)M(4E)A(S6) (1^V)(R3E)F(5)
SSTL, 1.35V
SSTL, 1.5V
SSTL, Class I and II, 1.8V
POD10, 1.0V
POD12, 1.2V
DIFF_HSTL, Class I, 1.2V
SSTL135, SSTL135_R V_REF – 0.575 V_REF + 0.575
SSTL15, SSTL15_R
V_REF – 0.65 V_REF + 0.65
SSTL18_I, SSTL18_II V_REF – 0.8 V_REF + 0.8
POD10
V_REF – 0.6 V_REF + 0.6
POD12
V_REF – 0.74 V_REF + 0.74
DIFF_HSTL_I_12
0.6 – 0.125 0.6 + 0.125
V_REF
V_REF
V_REF
V_REF
V_REF
0⁽⁶⁾
0.675
0.75
0.90
0.70
0.84
–
DIFF_HSTL, Class I and II,1.5V
DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_HSTL, Class I and II, 1.8V
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0⁽⁶⁾
–
DIFF_HSUL, 1.2V
DIFF_HSUL_12
0.6 – 0.125 0.6 + 0.125 0⁽⁶⁾
–
DIFF_SSTL, 1.2V
DIFF_SSTL12
0.6 – 0.125 0.6 + 0.125 0⁽⁶⁾
–
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL135,
DIFF_SSTL135_R
0.675 –
0.125
0.675 +
0.125
0⁽⁶⁾
–
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0⁽⁶⁾
–
DIFF_POD10, 1.0V
DIFF_POD10
0.70 – 0.125 0.70 + 0.125 0⁽⁶⁾
–
DIFF_POD12, 1.2V
DIFF_POD12
0.84 – 0.125 0.84 + 0.125 0⁽⁶⁾
–
LVDS (low-voltage differential signaling),
1.8V
LVDS
0.9 – 0.125 0.9 + 0.125 0⁽⁶⁾
–
LVDS_25, 2.5V
LVDS_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
SUB_LVDS, 1.8V
SUB_LVDS
0.9 – 0.125 0.9 + 0.125 0⁽⁶⁾
–
SLVS, 1.8V
SLVS_400_18
0.9 – 0.125 0.9 + 0.125 0⁽⁶⁾
–
SLVS, 2.5V
SLVS_400_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
LVPECL, 2.5
LVPECL
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
BLVDS_25, 2.5V
BLVDS_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
MINI_LVDS_25, 2.5V
MINI_LVDS_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
PPDS_25
PPDS_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
RSDS_25
RSDS_25
1.25 – 0.125 1.25 + 0.125 0⁽⁶⁾
–
TMDS_33
TMDS_33
3 – 0.125 3 + 0.125
0⁽⁶⁾
–
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same
voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the
same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between V_Land V_H.
3.
Measurements are made at
measurements. V_REF values
typical, minimum,
listed are typical.
and
maximum
V_REF
values.
Reported
delays
reflect
worst
case
of
these
4. Input voltage level from which measurement starts.
5.
This is an input
in Figure 1.
voltage
reference
that
bears
no
relation
to
the
V_REF/V_MEAS
parameters
found
in
IBIS
models
and/or
noted
6. The value given is the differential input voltage.
DS893 (v1.7.1) April 4, 2016
Product Specification
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