DS893 Datasheet, PDF (72/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Configuration Switching Characteristics
Table 86: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
T_PL
Program latency
T_POR
Power-on reset
(40 ms maximum ramp rate time)
Power-on reset with POR override
(2 ms maximum ramp rate time)
T_PROGRAM
Program pulse width
CCLK Output (Master Mode)
T_ICCK
T_MCCKL
T_MCCKH
Master CCLK output delay from INIT_B
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
SPI x2/x4/x8
BPI x8, x16
F_MCCK
Master CCLK
frequency
SPI x1 and serial
SLR-based devices
SPI x1 and serial
all other devices
SelectMAP
F_{MCCK_START}
Master CCLK frequency at start of
configuration
F_MCCKTOL
Frequency tolerance, master mode with
respect to nominal CCLK
CCLK Input (Slave Modes)
T_SCCKL
T_SCCKH
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Serial SLR-based
devices
F_SCCK
Slave CCLK frequency Serial all other
devices
SelectMAP
Speed Grades and V_CCINT
Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
7.5
7.5
7.5
7.5
57
57
57
57
0
0
0
0
15
15
15
15
5
5
5
5
250
250
250
250
150
40/60
40/60
150
100
150
125
3
±35
150
40/60
40/60
150
100
150
125
3
±35
150
40/60
40/60
150
100
150
125
3
±35
150
40/60
40/60
150
100
150
125
3
±35
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
100
100
100
100
150
150
150
150
125
125
125
125
Units
ms, Max
ms, Max
ms, Min
ms, Max
ms, Min
ns, Min
ns, Min
%, Min/Max
%, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Typ
%, Max
ns, Min
ns, Min
MHz, Max
MHz, Max
MHz, Max
DS893 (v1.7.1) April 4, 2016
Product Specification
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