DS893 Datasheet, PDF (63/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 72: GTY Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
Typ
Max Units
T_{J6.6_CPLL}
D_{J6.6_CPLL}
T_J5.0
D_J5.0
T_J4.25
D_J4.25
T_J4.00L
D_J4.00L
T_J3.75
D_J3.75
T_J3.20
D_J3.20
T_J2.5
D_J2.5
T_J1.25
D_J1.25
T_J500
D_J500
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
–
6.6 Gb/s
–
–
5.0 Gb/s
–
–
4.25 Gb/s
–
–
4.00 Gb/s
–
–
3.75 Gb/s
–
3.20 Gb/s⁽⁵⁾
–
–
2.5 Gb/s⁽⁶⁾
–
–
1.25 Gb/s⁽⁷⁾
–
–
–
500 Mb/s
–
–
0.30
UI
–
0.15
UI
–
0.30
UI
–
0.15
UI
–
0.30
UI
–
0.15
UI
–
0.32
UI
–
0.16
UI
–
0.20
UI
–
0.10
UI
–
0.20
UI
–
0.10
UI
–
0.20
UI
–
0.10
UI
–
0.15
UI
–
0.05
UI
–
0.10
UI
–
0.05
UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four fully-populated GTY Quads at maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
4. All jitter values are based on a bit-error ratio of 10^-12.
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
Table 73: GTY Transceiver Receiver Switching Characteristics
Symbol
Description
Condition
F_GTYRX
T_RXELECIDLE
Serial data rate
Time for RXELECIDLE to respond to loss or restoration of
data
R_XOOBVDPP
R_XSST
R_XRL
OOB detect threshold peak-to-peak
Receiver spread-spectrum tracking⁽¹⁾ Modulated at 33 kHz
Run length (CID)
Bit rates ≤ 6.6 Gb/s
R_XPPMTOL
Data/REFCLK PPM offset tolerance
Bit rates > 6.6 Gb/s
and ≤ 8.0 Gb/s
Bit rates > 8.0 Gb/s
SJ Jitter Tolerance⁽²⁾
J_{T_SJ30.5}
J_{T_SJ28.2}
Sinusoidal jitter (QPLL)⁽³⁾
Sinusoidal jitter (QPLL)⁽³⁾
30.5 Gb/s
28.2 Gb/s
Min
0.500
–
60
–5000
–
–1250
–700
–200
0.20
0.25
Typ
–
10
–
–
–
–
–
–
Max Units
F_GTYMAX Gb/s
–
ns
150
0
256
1250
mV
ppm
UI
ppm
700
ppm
200
ppm
–
–
UI
–
–
UI
DS893 (v1.7.1) April 4, 2016
Product Specification
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