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DS893 Datasheet, PDF (58/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics
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Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: GTY Transceiver Performance (Cont’d)
Symbol
Description
Outp
ut
Divid
er
Speed Grades and VCCINT Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
Unit
s
Min
Max
Min
Max
Min
Max
Min
Max
1(5)
16.0
26.0
16.0 26.0 16.0
26.0
N/A
N/A Gb/s
1(6)
8.0
13.0
8.0
13.0
8.0
13.0
8.0
12.5 Gb/s
FGTYQRANGE2
QPLL1 line rate
range
2(6)
4(6)
4.0
2.0
6.5
3.25
4.0
6.5
4.0
2.0
3.25
2.0
6.5
3.25
4.0
2.0
6.5
3.25
Gb/s
Gb/s
8(6)
1.0
1.625
1.0 1.625 1.0
1.625
1.0
1.625 Gb/s
16(6) 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
Min
Max
Min
Max
Min
Max
Min
Max
FCPLLRANGE CPLL frequency range
2.0
6.25
2.0
6.25
2.0
6.25
2.0
4.25 GHz
FQPLL0RANGE QPLL0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 GHz
FQPLL1RANGE QPLL1 frequency range 8.0
13.0
8.0
13.0
8.0
13.0
8.0
13.0 GHz
Notes:
1. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
2. The values listed are the rounded results of the calculated equation (2 x QPLL0_Frequency)/Output_Divider. These values
are for line rates greater than 16.375 Gb/s.
3. This value is limited by FGTYMAX.
4. The values listed are rounded results from calculated equation (QPLL0_Frequency)/Output_Divider.
5. The values listed are the rounded results of the calculated equation (2 x QPLL1_Frequency)/Output_Divider. These values
are for line rates greater than 16.375 Gb/s.
6. The values listed are rounded results from calculated equation (QPLL1_Frequency)/Output_Divider.
Table 67: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
Description
All Devices
Units
FGTYDRPCLK GTYDRPCLK maximum frequency
250
MHz
Table 68: GTY Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
Min
FGCLK
TRCLK
TFCLK
TDCREF
Reference clock frequency range
60
Reference clock rise time
20% – 80%
–
Reference clock fall time
80% – 20%
–
Reference clock duty cycle
Transceiver PLL only
40
Typ
–
200
200
50
Max
820
–
–
60
Units
MHz
ps
ps
%
X-Ref Target - Figure 8
80%
TRCLK
20%
TFCLK
ds893_05_120314
Figure 8: Reference Clock Timing Parameters
DS893 (v1.7.1) April 4, 2016
Product Specification
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