DS893 Datasheet, PDF (34/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard Attribute
SUB_LVDS
TMDS_33
SUB_LVDS
TMDS_33
Notes:
1. C_REF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
R_REF
(Ω)
100
50
C_REF(1)
(pF)
0
0
V_MEAS
(V)
0⁽²⁾
0⁽²⁾
V_REF
(V)
0
3.3
Block RAM and FIFO Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grades and
V_CCINT Operating
Voltages
1.0V
0.95V
Units
-3 -1H -2
-1
Maximum Frequency
F_{MAX_WF_NC}
Block RAM
(WRITE_FIRST and NO_CHANGE modes).
660 585 585 525 MHz
F_{MAX_RF}
F_{MAX_FIFO}
Block RAM (READ_FIRST mode).
575 510 510 460 MHz
FIFO in all modes without ECC.
660 585 585 525 MHz
Block RAM and FIFO in ECC configuration without
PIPELINE.
530
450
450
390
MHz
F_{MAX_ECC}
Block RAM and FIFO in ECC configuration with
PIPELINE and Block RAM in WRITE_FIRST or
NO_CHANGE mode.
660 585 585 525 MHz
Block RAM in ECC configuration in READ_FIRST
mode with PIPELINE.
575 510 510 460
MHz
F_{MAX_ADDREN_RDADDRCHANGE}
Block RAM with address enable and read address
change compare turned on.
575
510
510
460
MHz
T_{PW_WF_NC(1)}
Block RAM in WRITE_FIRST and NO_CHANGE
modes and FIFO. Clock High/Low pulse width.
758 855 855 952 ps, Min
T_{PW_RF(1)}
Block RAM in READ_FIRST modes.
Clock High/Low pulse width.
870 980 980 1087 ps, Min
Block RAM and FIFO Clock-to-Out Delays
T_{RCKO_DO}
Clock CLK to DOUT output (without output
register)
1.13 1.44 1.44 1.64 ns, Max
T_{RCKO_DO_REG}
Clock CLK to DOUT output (with output register) 0.37 0.44 0.44 0.49 ns, Max
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse width requirements at the higher
frequencies.
DS893 (v1.7.1) April 4, 2016
Product Specification
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