DS893 Datasheet, PDF (45/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
X-Ref Target - Figure 3
+V
P
N
0
X-Ref Target - Figure 4
+V
Figure 3: Single-Ended Peak-to-Peak Voltage
Single-Ended
Peak-to-Peak
Voltage
ds893_03_120314
Differential
0
Peak-to-Peak
Voltage
–V
P–N
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
Figure 4: Differential Peak-to-Peak Voltage
ds893_04_120314
Table 47 summarizes the DC specifications of the clock input of the GTH transceivers in Virtex UltraScale
FPGAs. Consult the UltraScale Architecture GTH Transceiver User Guide (UG576) for further details.
Table 47: GTH Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
V_IDIFF
R_IN
C_EXT
Differential peak-to-peak input voltage.
Differential input resistance.
Required external AC coupling capacitor.
Min
250
–
–
Typ
–
100
10
Max
2000
–
–
Units
mV
Ω
nF
Table 48: GTH Transceiver Clock Output Level Specification
Symbol
Description
Conditions
V_OL
V_OH
V_DDOUT
Output high voltage for P and N.
Output low voltage for P and N.
Differential output voltage: (P–
N), P = High
(N–P), N = High
R_T = 100Ω across P and N signals
R_T = 100Ω across P and N signals
R_T = 100Ω across P and N signals
V_CMOUT Common mode voltage.
R_T = 100Ω across P and N signals
Min
–
–
–
–
Typ
400
760
±360
580
Max
–
–
Units
mV
mV
–
mV
–
mV
DS893 (v1.7.1) April 4, 2016
Product Specification
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