DS893 Datasheet, PDF (57/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
X-Ref Target - Figure 7
+V
Differential
0
Peak-to-Peak
Voltage
–V
P–N
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
Figure 7: Differential Peak-to-Peak Voltage
ds893_04_120314
Table 65 summarizes the DC specifications of the clock input of the GTY transceivers in Virtex UltraScale
FPGAs. Consult www.xilinx.com/products/technology/high-speed-serial for further details.
Table 65: GTY Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
V_IDIFF
R_IN
C_EXT
Differential peak-to-peak input voltage
Differential input resistance
Required external AC coupling capacitor
Min
250
–
–
Typ
–
100
10
Max
2000
–
–
Units
mV
Ω
nF
GTY Transceiver Switching Characteristics
Consult www.xilinx.com/products/technology/high-speed-serial for further information.
Table 66: GTY Transceiver Performance
Symbol
Description
Outp
ut
Divid
er
Speed Grades and V_CCINT Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
Unit
s
F_GTYMAX
F_GTYMIN
GTY maximum line rate
GTY minimum line rate
30.5
0.5
Min
Max
25.8
0.5
Min
Max
28.21
0.5
Min
Max
12.5
0.5
Min
Max
Gb/s
Gb/s
1
4.0
12.5
4.0
12.5
4.0
12.5
4.0
8.5 Gb/s
2
2.0
6.25
2.0
6.25
2.0
6.25
2.0
4.25 Gb/s
F_GTYCRANGE
CPLL line rate
range⁽¹⁾
4
8
1.0
3.125
1.0 3.125 1.0
3.125
1.0
2.125 Gb/s
0.5 1.5625 0.5 1.5625 0.5 1.5625 0.5 1.0625 Gb/s
16
N/A
Gb/s
32
N/A
Gb/s
Min
Max
Min
Max
Min
Max
Min
1⁽²⁾ 19.6 30.5⁽³⁾ 19.6 25.8 19.6 28.21 N/A
Max
N/A
Gb/s
F_GTYQRANGE1
QPLL0 line rate
range
1⁽⁴⁾
2⁽⁴⁾
4⁽⁴⁾
8⁽⁴⁾
16⁽⁴⁾
9.8 16.375
4.9 8.1875
2.45 4.09375
1.225 2.04688
0.6125 1.02344
9.8 16.375 9.8 16.375 9.8
12.5
4.9 8.1875 4.9 8.1875 4.9 8.1875
2.45 4.09375 2.45 4.09375 2.45 4.09375
1.225 2.04688 1.225 2.04688 1.225 2.04688
0.6125 1.02344 0.6125 1.02344 0.6125 1.02344
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
DS893 (v1.7.1) April 4, 2016
Product Specification
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