DS893 Datasheet, PDF (20/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs
implemented in Virtex UltraScale FPGAs. These values are subject to the same guidelines as the AC
Switching Characteristics, page 17. In each table, the I/O bank type is either high performance (HP) or high
range (HR).
Table 23: LVDS Component Mode Performance
Description
I/O Bank
Type
HP
LVDS TX DDR (OSERDES 4:1, 8:1)
HR
HP
LVDS TX SDR (OSERDES 2:1, 4:1)
HR
LVDS RX DDR (ISERDES 1:4, 1:8)⁽¹⁾
HP
HR
LVDS RX SDR (ISERDES 1:2, 1:4)⁽¹⁾
HP
HR
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
1250
1250
1250
1250
1250
1250
1250
1000
625
625
625
625
625
625
625
500
1250
1250
1250
1250
1250
1250
1250
1000
625
625
625
625
625
625
625
500
Units
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
Table 24: LVDS Native Mode Performance⁽¹⁾
Description
I/O Bank
Type
LVDS TX DDR (TX_BITSLICE 4:1, 8:1)
HP
HR
LVDS TX SDR (TX_BITSLICE 2:1, 4:1)
HP
HR
LVDS RX DDR (RX_BITSLICE 1:4, 1:8)⁽²⁾
HP
HR
LVDS RX SDR (RX_BITSLICE 1:2, 1:4)⁽²⁾
HP
HR
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
-3
-1H
-2
-1
1600
1600
1600
1400
1250
1250
1250
1250
800
800
800
700
625
625
625
625
1600
1600
1600
1400
1250
1250
1250
1250
800
800
800
700
625
625
625
625
Units
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Notes:
1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite.
2. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
DS893 (v1.7.1) April 4, 2016
Product Specification
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