DS893 Datasheet, PDF (48/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 54: GTH Transceiver User Clock Switching Characteristics⁽¹⁾
Symbol
Description
Data Width Conditions
(Bit)
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
Internal Interconnec
Logic
t Logic
-3
-1H
-2
-1
F_TXOUTPMA
TXOUTCLK maximum frequency sourced from
OUTCLKPMA.
511.719
511.719
511.719
390.625
F_RXOUTPMA
RXOUTCLK maximum frequency sourced from
OUTCLKPMA.
511.719
511.719
511.719
390.625
F_TXOUTPROGDIV
TXOUTCLK maximum frequency sourced from
TXPROGDIVCLK.
511.719
511.719
511.719
511.719
F_RXOUTPROGDIV
RXOUTCLK maximum frequency sourced from
RXPROGDIVCLK.
511.719
511.719
511.719
511.719
F_TXIN
TXUSRCLK
maximum
frequency
16
16, 32
511.719 511.719 511.719 390.625
32
32, 64
511.719 511.719 511.719 390.625
20
20, 40
409.375 409.375 409.375 312.500
40
40, 80
409.375 409.375 409.375 312.500
F_RXIN
RXUSRCLK
maximum
frequency
16
16, 32
511.719 511.719 511.719 390.625
32
32, 64
511.719 511.719 511.719 390.625
20
20, 40
409.375 409.375 409.375 312.500
40
40, 80
409.375 409.375 409.375 312.500
16
16
511.719 511.719 511.719 390.625
F_TXIN2
TXUSRCLK2
maximum
frequency
16, 32
32
20
20, 40
32
511.719 511.719 511.719 390.625
64
255.860 255.860 255.860 195.313
20
409.375 409.375 409.375 312.500
40
409.375 409.375 409.375 312.500
40
80
204.688 204.688 204.688 156.250
16
16
511.719 511.719 511.719 390.625
F_RXIN2
RXUSRCLK2
maximum
frequency
16, 32
32
20
20, 40
32
511.719 511.719 511.719 390.625
64
255.860 255.860 255.860 195.313
20
409.375 409.375 409.375 312.500
40
409.375 409.375 409.375 312.500
40
80
204.688 204.688 204.688 156.250
Notes:
1. Clocking must be implemented as described in UltraScale Architecture GTH Transceiver User Guide (UG576).
Unit
s
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS893 (v1.7.1) April 4, 2016
Product Specification
www.xilinx.com
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