DS681 Datasheet, PDF (48/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
Master Serial and Slave Serial Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Input/Output)
DIN
(Input)
DOUT
(Output)
T_DCC
T_CCD
Bit 0
Bit 1
T_MCCL
T_SCCL
T_MCCH
T_SCCH
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
Figure 11: Waveforms for Master Serial and Slave Serial Configuration
DS312-3_05_103105
Table 49: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol
Description
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
Hold Times
T_CCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Clock Timing
T_CCH
High pulse width at the CCLK input pin
T_CCL
Low pulse width at the CCLK input pin
F_CCSER
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
Slave/
Master
Both
Both
Master
Slave
Master
Slave
Master
Slave
Slave
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
-4 Speed Grade
Min
Max
Units
1.5
10
ns
7
–
ns
0
ns
–
1.0
See Table 47
See Table 48
See Table 47
See Table 48
0
100
MHz
0
100
MHz
48
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DS681 (v1.1) February 3, 2009
Product Specification