DS681 Datasheet, PDF (2/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Key Feature Differences from Commercial XC Devices
• AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
• Guaranteed to meet full electrical specification over the
T_J = –40°C to +125°C temperature range (Q-Grade)
• XA Spartan-3A devices are available in the -4 speed
grade only
• PCI-66 is not supported in the XA Spartan-3A FPGA
product line
• Platform Flash is not supported within the XA family
• XA Spartan-3A devices are available in Pb-Free
packaging only.
• MultiBoot is not supported in XA versions of this
product.
• The XA Spartan-3A device must be power cycled prior
to reconfiguration.
Table 1: Summary of XA Spartan-3A FPGA Attributes
CLB Array
(One CLB = Four Slices)
Device
System Equivalent
Total Total Distributed
Gates Logic Cells Rows Columns CLBs Slices RAM bits⁽¹⁾
XA3S200A 200K 4,032 32 16 448 1,792 28K
XA3S400A 400K 8,064 40 24 896 3,584 56K
XA3S700A 700K 13,248 48 32 1,472 5,888 92K
XA3S1400A 1400K 25,344 72 40 2,816 11,264 176K
Block
RAM
bits⁽¹⁾
288K
360K
360K
576K
Dedicated
Multipliers
16
20
20
32
DCMs
4
4
8
8
Maximum
User I/O
195
311
372
375
Maximum
Differential
I/O Pairs
90
142
165
165
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
The XA Spartan-3A family architecture consists of five
fundamental programmable functional elements:
• Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
• Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
• Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
• Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
• Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.These elements are organized as shown in
Figure 1. A dual ring of staggered IOBs surrounds a
regular array of CLBs. Each device has two columns of
block RAM. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated
with a dedicated multiplier. The DCMs are positioned in
the center with two at the top and two at the bottom of
the device. The XA3S700A and XA3S1400A add two
DCMs in the middle of the two columns of block RAM
and multipliers. The XA Spartan-3A family features a
rich network of routing that interconnect all five
functional elements, transmitting signals among them.
Each functional element has an associated switch
matrix that permits multiple connections to the routing.
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DS681 (v1.1) February 3, 2009
Product Specification