DS681 Datasheet, PDF(45/56 Page) Xilinx, Inc – Fast look-ahead carry logic

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DS681 Datasheet, PDF (45/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Configuration and JTAG Timing

General Configuration Power-On/Reconfigure Timing

VCCINT

(Supply)

1.0V

1.2V

VCCAUX

(Supply)

2.0V

2.5V

3.3V

VCCO Bank 2

(Supply)

PROG_B

(Input)

INIT_B

(Open-Drain)

CCLK

(Output)

1.0V

TPOR

TPROG

TPL

TICCK

Notes:

1. The VCCINT, VCCAUX, and VCCO supplies can be applied in any order.

2. The Low-going pulse on PROG_B is optional after power-on.

3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

DS529-3_01_112906

Figure 10: Waveforms for Power-On and the Beginning of Configuration

Table 44: Power-On Timing and the Beginning of Configuration

Symbol

TPOR(2)

TPROG

TPL(2)

TINIT

TICCK(3)

Description

Device

The time from the application of VCCINT, VCCAUX, and VCCO All

Bank 2 supply voltage ramps (whichever occurs last) to the

rising transition of the INIT_B pin

The width of the low-going pulse on the PROG_B pin

All

The time from the rising edge of the PROG_B pin to the

rising transition on the INIT_B pin

XA3S200A

XA3S400A

XA3S700A

XA3S1400A

Minimum Low pulse width on INIT_B output

All

The time from the rising edge of the INIT_B pin to the

All

generation of the configuration clock signal at the CCLK

output pin

-4 Speed Grade

Min

Max

0.5

250

0.5

Units

Î¼s

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO,

and VCCAUX lines.

2. Power-on reset and the clearing of configuration memory occurs during this period.

3. This specification applies only to the Master Serial, SPI, and BPI modes.

DS681 (v1.1) February 3, 2009

www.xilinx.com

Product Specification

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