DS681 Datasheet, PDF (34/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 28: Recommended Number of Simultaneously
Switching Outputs per V_CCO-GND Pair
(V_CCAUX=3.3V)(Continued)
Package Type
FTG256, FGG400, FGG484
Signal Standard
(IOSTANDARD)
Top, Bottom
(Banks 0,2)
Left, Right
(Banks 1,3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
22
–
LVDS_33
27
–
BLVDS_25
4
4
MINI_LVDS_25
22
–
MINI_LVDS_33
27
–
LVPECL_25
LVPECL_33
RSDS_25
22
–
RSDS_33
27
–
TMDS_33
27
–
PPDS_25
22
–
PPDS_33
27
–
Table 28: Recommended Number of Simultaneously
Switching Outputs per V_CCO-GND Pair
(V_CCAUX=3.3V)(Continued)
Package Type
FTG256, FGG400, FGG484
Signal Standard
(IOSTANDARD)
Top, Bottom
(Banks 0,2)
Left, Right
(Banks 1,3)
DIFF_HSTL_I
–
10
DIFF_HSTL_III
–
4
DIFF_HSTL_I_18
8
8
DIFF_HSTL_II_18
–
2
DIFF_HSTL_III_18
5
4
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–
4
DIFF_SSTL2_I
9
9
DIFF_SSTL2_II
–
4
DIFF_SSTL3_I
4
5
DIFF_SSTL3_II
3
3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V_IL/V_IH voltage
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
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DS681 (v1.1) February 3, 2009
Product Specification