DS681 Datasheet, PDF (44/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
Suspend Mode Timing
Entering Suspend Mode
SUSPEND Input
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
t_{SUSPENDHIGH_AWAKE}
t_{SUSPENDLOW_AWAKE}
t_{SUSPEND_GWE}
t_{AWAKE_GWE}
Write Protected
t_{SUSPEND_GTS}
Defined by SUSPEND constraint
t_{AWAKE_GTS}
t_{SUSPEND_DISABLE}
Blocked
t_{SUSPEND_ENABLE}
Figure 9: Suspend Mode Timing
DS610-3_08_061207
Table 43: Suspend Mode Timing Parameters
Symbol
Description
Min Typ Max
Entering Suspend Mode
T_{SUSPENDHIGH_AWAKE} Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter –
7
–
(suspend_filter:No)
T_{SUSPENDFILTER}
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
+160 +300 +600
T_{SUSPEND_GWE}
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
T_{SUSPEND_GTS}
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
<5
–
T_{SUSPEND_DISABLE}
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
–
340
–
Exiting Suspend Mode
T_{SUSPENDLOW_AWAKE} Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not – 4 to 108 –
include DCM lock time.
T_{SUSPEND_ENABLE}
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
– 3.7 to –
109
T_{AWAKE_GWE1}
Rising edge of the AWAKE pin until write-protect lock released on all writable –
67
–
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
T_{AWAKE_GWE512}
Rising edge of the AWAKE pin until write-protect lock released on all writable –
14
–
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
T_{AWAKE_GTS1}
Rising edge of the AWAKE pin until outputs return to the behavior described –
57
–
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
T_{AWAKE_GTS512}
Rising edge of the AWAKE pin until outputs return to the behavior described –
14
–
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
Units
ns
ns
ns
ns
ns
μs
μs
ns
μs
ns
μs
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
44
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DS681 (v1.1) February 3, 2009
Product Specification