DS681 Datasheet, PDF (19/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
Setup Times
T_IOPICK
Time from the setup of data at the Input pin LVCMOS25⁽²⁾
to the active transition at the ICLK input of
the Input Flip-Flop (IFF). No Input Delay is
programmed.
T_IOPICKD
Time from the setup of data at the Input pin LVCMOS25⁽²⁾
to the active transition at the ICLK input of
the Input Flip-Flop (IFF). The Input Delay is
programmed.
IFD_
DELAY_
VALUE
Device
Speed Grade
-4
Min
Units
0
XA3S200A
1.81
ns
XA3S400A
1.51
ns
XA3S700A
1.51
ns
XA3S1400A
1.74
ns
1
XA3S200A
2.20
ns
2
2.93
ns
3
3.78
ns
4
4.37
ns
5
4.20
ns
6
5.23
ns
7
6.11
ns
8
6.71
ns
1
XA3S400A
2.02
ns
2
2.67
ns
3
3.43
ns
4
3.96
ns
5
3.95
ns
6
4.81
ns
7
5.66
ns
8
6.19
ns
1
XA3S700A
1.95
ns
2
2.83
ns
3
3.72
ns
4
4.31
ns
5
4.14
ns
6
5.19
ns
7
6.10
ns
8
6.73
ns
1
XA3S1400A
2.17
ns
2
2.92
ns
3
3.76
ns
4
4.32
ns
5
4.19
ns
6
5.09
ns
7
5.98
ns
8
6.57
ns
DS681 (v1.1) February 3, 2009
www.xilinx.com
19
Product Specification