DS681 Datasheet, PDF (17/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Clock-to-Output Times
T_ICKOFDCM
When reading from the Output Flip-Flop
(OFF), the time from the active transition on
the Global Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, with DCM⁽³⁾
T_ICKOF
When reading from OFF, the time from the
active transition on the Global Clock pin to
data appearing at the Output pin. The DCM is
not in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, without DCM
Device
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
Speed Grade
-4
Max
Units
3.27
ns
3.33
ns
3.50
ns
3.99
ns
5.24
ns
5.12
ns
5.34
ns
5.69
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25.
3. DCM output jitter is included in all measurements.
DS681 (v1.1) February 3, 2009
www.xilinx.com
17
Product Specification