DS681 Datasheet, PDF (22/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
Table 21: Propagation Times for the IOB Input Path (Continued)
Symbol
T_IOPLID
Description
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
Conditions
LVCMOS25⁽²⁾
IFD_
DELAY_
VALUE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Device
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
Speed Grade
-4
Max
2.43
3.16
4.01
4.60
4.43
5.46
6.33
6.94
2.25
2.90
3.66
4.19
4.18
5.03
5.88
6.42
2.18
3.06
3.95
4.54
4.37
5.42
6.33
6.96
2.40
3.15
3.99
4.55
4.42
5.32
6.21
6.80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 22.
22
www.xilinx.com
DS681 (v1.1) February 3, 2009
Product Specification