DS681 Datasheet, PDF (3/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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IOBs
CLB
DCM
IOBs
DCM
CLBs
DCM
IOBs
DS312-1_01_032606
Notes:
1. The XA3S700A and XA3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines.
Figure 1: XA Spartan-3A Family Architecture
Configuration
XA Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a SPI serial Flash
or some other non-volatile medium, either on or off the
board. After applying power, the configuration data is written
to the FPGA using any of five different modes:
• Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
• Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
• Slave Serial, typically downloaded from a processor
• Slave Parallel, typically downloaded from a processor
• Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Additionally, each XA Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
DS681 (v1.1) February 3, 2009
www.xilinx.com
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Product Specification