DS681 Datasheet, PDF (21/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 20: Setup and Hold Times for the IOB Input Path (Continued)
Symbol
Description
Set/Reset Pulse Width
T_{RPW_IOB}
Minimum pulse width to SR control input
on IOB
Conditions
IFD_
DELAY_
VALUE
Device
All
Speed Grade
-4
Min
Units
1.61
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Input Propagation Times
Table 21: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
Propagation Times
T_IOPLI
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
LVCMOS25⁽²⁾
IFD_
DELAY_
VALUE
0
Device
Speed Grade
-4
Max
Units
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
2.04
ns
1.74
ns
1.74
ns
1.97
ns
DS681 (v1.1) February 3, 2009
www.xilinx.com
21
Product Specification