DS681 Datasheet, PDF (47/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
Minimum
F_CCLK1
Equivalent CCLK clock frequency
1
by ConfigRate setting
(power-on value)
I-Grade &
Q-Grade
0.40
F_CCLK3
3
I-Grade &
Q-Grade
1.20
F_CCLK6
6
I-Grade &
Q-Grade
2.40
F_CCLK7
7
I-Grade &
Q-Grade
2.80
F_CCLK8
8
I-Grade &
Q-Grade
3.20
F_CCLK10
10
I-Grade &
Q-Grade
4.00
F_CCLK12
12
I-Grade &
Q-Grade
4.80
F_CCLK13
13
I-Grade &
Q-Grade
5.20
F_CCLK17
17
I-Grade &
Q-Grade
6.80
F_CCLK22
22
I-Grade &
Q-Grade
8.80
F_CCLK25
25
I-Grade &
Q-Grade
10.00
F_CCLK27
27
I-Grade &
Q-Grade
10.80
F_CCLK33
33
I-Grade &
Q-Grade
13.20
F_CCLK44
44
I-Grade &
Q-Grade
17.60
F_CCLK50
50
I-Grade &
Q-Grade
20.00
F_CCLK100
100
I-Grade &
Q-Grade
40.00
Maximum
0.95
2.85
5.74
6.74
7.58
9.65
11.48
12.49
16.33
21.23
23.59
28.31
32.67
42.47
53.08
106.16
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 47: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
Symbol
Description
1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Units
Master Mode
T_MCCL,
T_MCCH
CCLK
Minimum Low
I-Grade &
Q-Grade
474 158 78.4 66.8 59.3 46.6 39.2 36.0 27.6 21.2 19.1 15.9 13.8 10.6 8.5
4.2
ns
and High Time
Table 48: Slave Mode CCLK Input Low and High Time
Symbol
Description
T_SCCL,
T_SCCH
CCLK Low and High time
Min
Max
Units
5
∞
ns
DS681 (v1.1) February 3, 2009
www.xilinx.com
47
Product Specification