DS681 Datasheet, PDF (18/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Setup Times
T_PSDCM
T_PSFD
Description
Conditions
When writing to the Input Flip-Flop (IFF),
the time from the setup of data at the Input
pin to the active transition at a Global Clock
pin. The DCM is in use. No Input Delay is
programmed.
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
When writing to IFF, the time from the setup
of data at the Input pin to an active transition
at the Global Clock pin. The DCM is not in
use. The Input Delay is programmed.
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 5,
without DCM
Hold Times
T_PHDCM
T_PHFD
When writing to IFF, the time from the active
transition at the Global Clock pin to the
point when data must be held at the Input
pin. The DCM is in use. No Input Delay is
programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
When writing to IFF, the time from the active
transition at the Global Clock pin to the
point when data must be held at the Input
pin. The DCM is not in use. The Input Delay
is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 5,
without DCM
Device
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
Speed Grade
-4
Min
2.84
2.68
2.57
2.17
2.76
2.60
2.63
2.41
-0.52
-0.29
-0.12
0.00
-0.56
-0.42
-0.75
-0.69
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input.
If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
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DS681 (v1.1) February 3, 2009
Product Specification