DS681 Datasheet, PDF (20/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 20: Setup and Hold Times for the IOB Input Path (Continued)
Symbol
Hold Times
T_IOICKP
Description
Conditions
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the
point where data must be held at the Input
pin. No Input Delay is programmed.
LVCMOS25⁽²⁾
T_IOICKPD
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the
point where data must be held at the Input
pin. The Input Delay is programmed.
LVCMOS25⁽²⁾
IFD_
DELAY_
VALUE
Device
Speed Grade
-4
Min
Units
0
XA3S200A
–0.65
ns
XA3S400A
–0.42
ns
XA3S700A
–0.67
ns
XA3S1400A
–0.71
ns
1
XA3S200A
–1.51
ns
2
–2.09
ns
3
–2.40
ns
4
–2.68
ns
5
–2.56
ns
6
–2.99
ns
7
–3.29
ns
8
–3.61
ns
1
XA3S400A
–1.12
ns
2
–1.70
ns
3
–2.08
ns
4
–2.38
ns
5
–2.23
ns
6
–2.69
ns
7
–3.08
ns
8
–3.35
ns
1
XA3S700A
–1.67
ns
2
–2.27
ns
3
–2.59
ns
4
–2.92
ns
5
–2.89
ns
6
–3.22
ns
7
–3.52
ns
8
–3.81
ns
1
XA3S1400A
–1.60
ns
2
–2.06
ns
3
–2.46
ns
4
–2.86
ns
5
–2.88
ns
6
–3.24
ns
7
–3.55
ns
8
–3.89
ns
20
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DS681 (v1.1) February 3, 2009
Product Specification