DS681 Datasheet, PDF (38/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 33: 18 x 18 Embedded Multiplier Timing (Continued)
Symbol
Description
Clock Frequency
F_MULT
Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG
input registers and the PREG output register⁽¹⁾
Speed Grade
-4
Min
Max
0
250
Notes:
1. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. The numbers in this table are based on the operating conditions set forth in Table 8.
Units
MHz
Block RAM Timing
Table 34: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_RCKO
When reading from block RAM, the delay from the active transition at the CLK input
to data appearing at the DOUT output
Setup Times
T_{RCCK_ADDR} Setup time for the ADDR inputs before the active transition at the CLK input of the
block RAM
T_{RDCK_DIB} Setup time for data at the DIN inputs before the active transition at the CLK input of
the block RAM
T_{RCCK_ENB} Setup time for the EN input before the active transition at the CLK input of the block
RAM
T_{RCCK_WEB} Setup time for the WE input before the active transition at the CLK input of the block
RAM
Hold Times
T_{RCKC_ADDR} Hold time on the ADDR inputs after the active transition at the CLK input
T_{RCKD_DIB} Hold time on the DIN inputs after the active transition at the CLK input
T_{RCKC_ENB} Hold time on the EN input after the active transition at the CLK input
T_{RCKC_WEB} Hold time on the WE input after the active transition at the CLK input
Clock Timing
T_BPWH
High pulse width of the CLK signal
T_BPWL
Low pulse width of the CLK signal
Clock Frequency
F_BRAM
Block RAM clock frequency
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Speed Grade
-4
Min
Max
–
2.49
0.36
–
0.31
–
0.77
–
1.26
–
0
–
0
–
0
–
0
–
1.79
–
1.79
–
0
280
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
38
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DS681 (v1.1) February 3, 2009
Product Specification