DS681 Datasheet, PDF (41/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

R
Digital Frequency Synthesizer
Table 37: Recommended Operating Conditions for the DFS
Symbol
Input Frequency Ranges⁽²⁾
F_CLKIN
CLKIN_FREQ_FX
Input Clock Jitter Tolerance⁽³⁾
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Description
Frequency for the CLKIN input
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
Period jitter at the CLKIN input
F_CLKFX < 150 MHz
F_CLKFX > 150 MHz
Speed Grade
-4
Min Max
0.200 333
–
±300
–
±150
–
±1
Units
MHz
ps
ps
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications
in Table 35.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Table 38: Switching Characteristics for the DFS
Speed Grade
-4
Symbol
Description
Device Min Max Units
Output Frequency Ranges
CLKOUT_FREQ_FX⁽²⁾
Output Clock Jitter^(3,4)
Frequency for the CLKFX and CLKFX180 outputs
All
5
320 MHz
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs.
CLKIN
≤ 20 MHz
All
Typ Max
Use the
ps
Spartan-3A Jitter
Calculator:
www.xilinx.com/s
upport/document
ation/data_sheets
/s3a_jitter_calc.zi
p
Duty Cycle^(5,6)
CLKIN
> 20 MHz
±[1% of ±[1% of ps
CLKFX CLKFX
period period
+ 100] + 200]
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
All
±[1% of ps
including the BUFGMUX and clock tree duty-cycle distortion
–
CLKFX
period
+ 350]
Phase Alignment⁽⁶⁾
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL CLK0 All
output when both the DFS and DLL are used
–
±200 ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL All
CLK0 output when both the DFS and DLL are used
±[1% of ps
–
CLKFX
period
+ 200]
DS681 (v1.1) February 3, 2009
www.xilinx.com
41
Product Specification